This relates to solid-state image sensor arrays and, more specifically, to image sensors with small size pixels that are illuminated from the back side of a pixel substrate. Small pixel sizes reduce the cost of manufacturing image sensor arrays, but it is important not to sacrifice image sensor performance when pixel size is reduced.
Conventional complementary metal-oxide-semiconductor (CMOS) image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. Upon completion of each integration cycle, the collected charge is converted into voltage signals, which are supplied to corresponding output terminals associated with the image sensor. Typically, the charge-to-voltage conversion is performed directly within the pixels, and the resulting analog pixel voltage signals are transferred to the output terminals through various pixel addressing and scanning schemes. The analog voltage signal can sometimes be converted on-chip to a digital equivalent before being conveyed off-chip. Each pixel includes a buffer amplifier (i.e., source follower) that drives output sensing lines that are connected to the pixels via respective address transistors.
After the charge-to-voltage conversion is complete and after the resulting signals are transferred out from the pixels, the pixels are reset before a subsequent integration cycle begins. In pixels that include floating diffusions (FD) serving as the charge detection node, this reset operation is accomplished by momentarily turning on a single reset transistor that connects the floating diffusion node to a voltage reference for draining (or removing) any charge transferred to the FD node. However, removing charge from the floating diffusion node using the reset transistor generates kTC-reset noise, as is well known in the art. This kTC noise must be removed using correlated double sampling (CDS) signal processing techniques in order to achieve desired low noise performance. Typical CMOS image sensors that utilize CDS require at least three transistors (3T) or four transistors (4T) per pixel. An example of the 4T pixel circuit with a pinned photodiode can be found in Lee (U.S. Pat. No. 5,625,210), incorporated herein as a reference.
A cross-sectional side view of a conventional pixel 100 is shown in FIG. 1. Pixel 100 is formed in substrate 101. Pixel substrate 101 includes p+ doped layer 102 deposited on the back surface of pixel substrate 101, which prevents the generation of excessive dark current by interface states. Substrate 101 includes epitaxial p-type doped layer 115 formed on top of p+ layer 102. Photons 90 that enter p-type doped layer 115 generate carriers that are collected in the potential well of the photodiode formed in region 108 at the front surface of substrate 101. The front (upper) surface of epitaxial p-type doped layer 115 is covered by oxide layer 109 that isolates doped poly-silicon charge transfer (TX) gate 110 from substrate 101. Transfer gate 110 includes masking oxide 111 deposited on an upper surface of transfer gate 110 that serves as a patterning hard mask as well as an additional blocking mask for ion implantation that forms the photodiode storage region.
The photodiode is formed by the p+ type doped potential pinning layer 107 and n-type doped layer 108 at the front surface of substrate 101. P+ type doped layer 107 reduces dark current generated by the interface states. Charge generated by impinging photons 90 is accumulated at region 108. Gate 110 includes sidewall spacers 116 formed on each side of gate 110 to control the mutual edge positions of p+ type doped layer 107 and charge storage layer 108. Floating diffusion (FD) diode 104 formed at the front surface of substrate 101 senses charge transferred from region 108 (i.e., as shown by arrow 121, charge is transferred from region 108 at the front side of pixel substrate 101 to region 104 at the front side of pixel substrate 101). Floating diffusion 104 is connected to a source follower (SF) transistor (not shown). The floating diffusion diode, source follower, and other pixel circuit components are built within p-type doped well 103.
The pixels are isolated from each other by p+ type doped regions 105 and 106 that may extend through epitaxial p-type doped layer 115 down to p+ type doped layer 102. The pixel is covered by inter-level (IL) oxide layers 112 (only one inter-level oxide layer is shown) that are used for the pixel metal wiring and interconnect isolation. The active pixel circuit components are connected to the wiring by metal via 114 deposited through contact holes 113.
As shown in drawing 100, a large portion of valuable pixel area is occupied by transfer gate 110. Other pixel circuit components (not shown) also occupy a large portion of the pixel, so there is not enough substrate area left for the photodiode that is disposed in a lateral direction from gate 110. This can lead to low photodiode charge storage capacity, poor pixel dynamic range, and poor noise performance.
These problems are amplified when pixel 100 is operated in a global shutter mode. To operate conventional pixel 100 in global shutter mode, an additional pinned diode and an additional transfer gate are typically formed at the front surface of substrate 101 adjacent to the photodiode formed by layers 107 and 108, as can be found in Yasutomi et al. (ISSCC Digest of Technical Papers, Feb. 10, 2010, pp. 398 and 399, entitled “A 2.7e Temporal Noise 99.7% Shutter Efficiency 92 dB Dynamic Range CMOS Image Sensor with Dual Global Shutter Pixels”). This is a modification of the well-known Interline Transfer Charge Coupled Device (CCD) concept, where charge from the pixel photodiodes is transferred first to vertical CCD registers located in the spaces between the pixels, then in parallel row-by-row to a serial register, which is then followed by a CCD transfer out to a common single charge detection node connected to an amplifier.
In conventional image sensors, kTC-noise reduction is sometimes performed using feedback capacitors formed within the pixel, as can be found in Takayanagi et al. (IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, 2001, entitled “A Four-Transistor Capacitive Feedback Reset Active Pixel and its Reset Noise Reduction Capability”). However, when feedback is performed within the pixels, the pixel circuit components occupy an even greater portion of the pixel, which can lead to further reduction in photodiode charge storage capacity, pixel dynamic range, and noise performance.
In some cases, two pixel substrates are stacked on top of each other, with one substrate having a built in photodiode and the other substrate carrying the rest of the pixel circuits. An example of two substrate stacked pixel a can be found in http://www.sony.net/SonyInfo/News/Press/201201/12-009E/ by Sony. However, when stacking the two substrates, the substrates must be electrically connected using wafer-to-wafer contacts and must be precisely aligned, resulting in increased fabrication difficulty and high manufacturing costs.
It would therefore be desirable to be able to provide improved image sensors without a stacking requirement.